PCM1795DB datasheet(46/68 Pages) TI2

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BitClock

DSDDecoder

DATA

BCK

SCK

ZEROL

ZEROR

MSEL

LRCK

PCM1796

DATA_L

DATA_R

PCM1795

SLES248A – MAY 2009 – REVISED MARCH 2015

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8.2.3 Application for DSD Format (DSD Mode) Interface

Figure 63 shows a connection diagram for DSD mode.

Figure 63. Connection Diagram in DSD Mode

8.2.3.1 Design Requirements

•

Control: Host controller with SPI communication

•

Audio Output: I/V output circuitry

•

Audio Input: DSD Digital Audio input

8.2.3.2 Detailed Design Procedure

8.2.3.2.1

Features

This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD™ (SACD)

applications.

The DSD mode is accessed by programming the following bit in the corresponding control register.

•

DSD = 1 (register 20)

The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.

Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.

The DSD bit must be set before inputting DSD data; otherwise, the PCM1795 erroneously detects the TDMCA

mode and commands are not accepted through the serial control interface.

8.2.3.2.2

Pin Assignment When Using DSD Format Interface

Several pins are redefined for DSD mode operation. These include:

•

DATA (pin 5): DSDL as left-channel DSD data input

•

LRCK (pin 4): DSDR as right-channel DSD data input

•

SCK (pin 7): DBCK as bit clock for DSD data

•

BCK (pin 6): Set low (N/A)

8.2.3.2.3

Requirements for System Clock

For operation in DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1795. The frequency of the bit

clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.

The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time

specifications shown in Figure 65 and Table 36.

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