PCM5142PW datasheet(5/123 Pages) TI2

5 / 123 page

PCM5141, PCM5142

www.ti.com

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

Pin Functions (continued)

MODE, NO.

I/O

DESCRIPTION

NAME

I2C

SPI

SDA

–

I/O

I2C

Data for I2C(1)(2)

MOSI

–

SPI

Input data for SPI(2)

ATT2

–

Digital gain and attenuation control pin

SCL

–

I2C

Input clock for I2C(2)

–

SPI

Input clock for SPI(2)

ATT1

–

Digital gain and attenuation control pin

GPIO5

–

I2C, SPI General purpose digital input and output port (3)

I/O

ATT0

–

Digital gain and attenuation control pin

GPIO4

–

I2C, SPI General purpose digital input and output port (3)

I/O

I2S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low)

MAST

–

BCK/LRCK inputs

GPIO3

–

I2C, SPI General purpose digital input and output port (3)

I/O

Analog gain selector : 0-dB 2-VRMS output (Low), –6-dB 1-VRMS output

AGNS

–

(High)

ADR2

–

I2C

2nd LSB address select bit for I2C

I/O

GPIO2

–

SPI

General purpose digital input and output port

DOUT

–

General Purpose Output (Low level)

Mode control selection pin (2)

MODE1 = Low, MODE2 = Low : Hardwired mode

MODE1

MODE1 = Low, MODE2 = High: I2C mode

MODE1 = High: SPI mode

I2C,

MODE2

–

MODE2

–

SPI

MS pin (chip select for SPI)

GPIO6

–

I/O

I2C, SPI General purpose digital input and output port

FLT

–

Filter select : Normal latency (Low) / Low latency (High)

SCK

System clock input(2)

BCK

I/O

Audio data bit clock input (slave) or output (master)(2)

DIN

Audio data input(2)

LRCK

I/O

Audio data word clock input (slave) or output (master)(2)

ADR1

–

I2C

LSB address select bit for I2C

Primary output data for SPI readback. Secondary; general purpose digital

MISO (GPIO1)

–

I/O

SPI

input/output port controlled by register

FMT

–

Audio format selection : I2S (Low) / Left justified (High)

XSMT

Soft mute control Soft mute(2) (Low) / soft un-mute (High)

LDOO

Internal logic supply rail terminal for decoupling, 1.8 V

DGND

Digital ground

DVDD

Digital power supply, 3.3 V or 1.8 V

(1)

Open-drain configuration in out mode.

(2)

Failsafe LVCMOS Schmitt trigger input.

(3)

Internal Pulldown

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