TLVM13640 datasheet(29/43 Pages) TI2

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8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Output Voltage Setpoint

The output voltage of the TLVM13630 device is externally adjustable using a resistor divider. The recommended

value of RFBB is 10 kΩ. Calculate the value for RFBT using Equation 9:

(9)

For the desired output voltage of – 5 V, enter the absolute value of 5 V for the VOUT in Equation 9. The formula

yields a value of 40.2 kΩ. Choose the closest available standard value of 40.2 kΩ for RFBT.

8.2.2.2.2 IBB Maximum Output Current

The achievable output current with an IBB topology using the TLVM13630 is IOUT(max) = ILDC(max) × (1 – D),

where ILDC(max) = 3 A is the rated current of the module and D = |VOUT| / (VIN + |VOUT|) is the module duty cycle.

Therefore in the case of VIN = 12 V and the VOUT = –5 V, the maximum output current is 2.1 A.

8.2.2.2.3 Switching Frequency Selection

To set the switching frequency to 1 MHz, connect a 13.0-kΩ resistor between the RT pin and AGND pins of the

module based on Equation 5.

8.2.2.2.4 Input Capacitor Selection

The TLVM13630 requires a minimum input capacitance of 2 × 4.7-µF ceramic type between the VIN pins and

PGND pins as close as possible to the module. High-quality ceramic type capacitors with sufficient voltage and

temperature rating are required. In the inverting buck-boost configuration the maximum voltage between VIN and

PGND pin of the module is equal to VIN + |VOUT|.

For this design, two 4.7-µF, 50-V, 1210 case size, ceramic capacitors are selected.

8.2.2.2.5 Output Capacitor Selection

The TLVM13630 requires a minimum of 25 µF of effective output capacitance for proper operation. High-

quality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output

capacitance can be added to reduce ripple voltage or for applications with transient load requirements.

For this design example, a two 47-µF, 10-V, 1210 case size, ceramic capacitors are used which have a total

effective capacitance of approximately 48 µF at 5 V.

8.2.2.2.6 Other Connections

Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.

The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it

does not appear at low frequency for a –5 V output and thus has minimal effect on the loop response for this

application.

In the inverting buck-boost configuration, the input capacitor CIN and output capacitor COUT can formed an AC

capacitive divider during a fast VIN transient or hot-plugged event at the input. This event will resulted in a

positive voltage spike at the output that may disturb the load. In this case, an optional Schottky diode may be

installed between –VOUT and GND as shown in Figure 8-12 to clamp the output spike.

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TLVM13630

SLVSFT6B – MAY 2021 – REVISED JANUARY 2022

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TLVM13640 Datasheet(PDF) 29 Page - Texas Instruments