TLVM13640 datasheet(34/43 Pages) TI2

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10 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal

thermal performance, and minimal generation of unwanted EMI.

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 10-1 and

Figure 10-2 show a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

• Place ceramic input and output capacitors close to the device pins to minimize high-frequency noise.

• Locate additional output capacitors between the ceramic capacitors and the load.

• Connect AGND to PGND at a single point.

• Place RFBT and RFBB as close as possible to the FB pin.

• Use multiple vias to connect the power planes to internal layers.

10.2 Layout Example

Figure 10-1. Typical Top-Layer Layout

Figure 10-2. Typical Top-Layer

10.2.1 Package Specifications

Table 10-1. Package Specifications Table

TPSM63603

VALUE

UNIT

Weight

123

Flammability

Meets UL 94 V-0

MTBF calculated reliability

Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign

MHrs

TLVM13630

SLVSFT6B – MAY 2021 – REVISED JANUARY 2022

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TLVM13640 Datasheet(PDF) 34 Page - Texas Instruments