TMDS442 datasheet(2/47 Pages) TI2

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TMDS442

SLLS757A – AUGUST 2006 – REVISED MARCH 2007

A precision resistor is connected externally from the VSADJ pin to ground, for setting the differential output

voltage to be compliant with the TMDS standard for all TMDS driver outputs. The PRE pin controls the TMDS

output to be operated under either a standard TMDS mode or an AC de-emphasis mode. When PRE = high, a

3-dB AC de-emphasis TMDS output swing is selected to pre-condition the output signals to overcome signal

impairments that may exist between the output of the TMDS442 and the HDMI receiver placed at a remote

location.

Each sink output port can be configured with the SA, SB, OE, I2CEN, and PRE pins. SA1, SB1, OE1, I2CEN1,

and PRE1 regulate the behaviour of sink port 1; SA2, SB2, OE2, I2CEN2, and PRE2 regulate the behaviour of

sink port 2. These control signals are hard-wire controlled by GPIO interface, or through a local I2C interface.

When GE = low, the configurations are done through a local I2C interface, LC_SCL, LC_SDA, LC_A0, and

LC_A1 pins, and the 5V_EN can be programmed through the local I2C interface. It is default high after device

powered on. When GE = high, the configurations are done through GPIO pins regardless the value of the 5V_EN

in the internal I2C registers.

The two bit source selector pins, SA and SB, determine the source transferred to the sink port. The internal

multiplexer interconnects the TMDS channels and I2C interface from the selected source port to the sink port.

The HPD output of the selected source port follows the status of the HPD_SINK. Since two of the source ports

will always be unconnected to any output, the I2C interfaces of unselected ports are isolated and the HPD

outputs of an unselected port are pulled low.

The TMDS outputs of each of the sink ports are enabled based on the OE signal and 5V_PWR signal (from the

selected source port). When OE is low, for an output port, and the 5V_PWR signal from the selected source port

is high, the TMDS output signals are enabled; otherwise they are disabled, and high impedance.

The I2C driver at sink side, SCL_SINK and SDA_SINK, are enabled by setting I2CEN high. When I2CEN is low,

the I2C driver can not forward a low state to the I2C bus connected at the sink port. A hard wire output voltage

select pin, OVS, allows adjustable output voltage level to SCL_SINK and SDA_SINK to optimise noise margins

while interfacing to different HDMI receivers. The I2C driver of each source port, SCL and SDA, is controlled by

its 5V_PWR signal. A valid 5-V signal appearing at the input of 5V_PWR enables the I2C driver of the source

port.

The device is packaged in a 128-pin PowerPAD TQFP package and characterized for operation from 0

°C to

°C.

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