TMDS442 datasheet(28/47 Pages) TI2

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Example - Writing to the TMDS442

TMDS442

SLLS757A – AUGUST 2006 – REVISED MARCH 2007

Table 3. TMDS442 Sink Port Register Bit Decoder (continued)

BIT

FUNCTION

BIT VALUES

RESULT

Source port 1 select

Source port 2 select

1, 0

SB SA

Source port 3 select

Source port 4 select

Bits 7 (MSB), 6 and 5 – Reserved bits without function.

Bit 4 – Controls the TMDS output differential voltage.

Bit 3 – Controls the status of DDC interface, SCL_SINK and

SDA_SINK.

Bit 2 – Controls the status of TMDS interface, Y/Z.

Bits 1, and 0 (LSB) – Selects the source input of the TMDS442.

The 5-V plug in status can be read through each bit of the sub-address (source plug-in status) status register.

Each bit of the third sub-address, source plug-in status registers, allows the user to read the cable plug-in status

based on the appearance of a valid +5-V power signal from each source input port. The bit description is

decoded in Table 4.

Table 4. TMDS442 Source Plug-In Status Register Bit Decoder

BIT

FUNCTION

BIT VALUES

RESULT

7, 6

Reserved

0 0

Default value

Sink port1 is the main display when the same source is selected by both sinks

Sink port2 is the main display when the same source is selected by both sinks

TMDS output status is not controlled by the corresponding +5-V power signal

5V_EN

TMDS output status is controlled by the corresponding +5-V power signal

Source side I2C buffer is disabled (Hi-Z) When source port 4 is selected by sink,

TMDS is Hi-Z

5V_PWR4

Source side I2C buffer is enabled When source port 4 is selected by sink, TMDS is

under the control of OE

Source side I2C buffer is disabled (Hi-Z)

5V_PWR3

When source port 3 is selected by sink, TMDS is Hi-Z

Source side I2C buffer is disabled (Hi-Z) When source port 2 is selected by sink,

TMDS is Hi-Z

5V_PWR2

Source side I2C buffer is enabled When source port 2 is selected by sink, TMDS is

under the control of OE

Source side I2C buffer is disabled (Hi-Z) When source port 1 is selected by sink,

TMDS is Hi-Z

5V_PWR1

Source side I2C buffer is enabled When source port 1 is selected by sink, TMDS is

under the control of OE

The proper way to write to the TMDS442 is illustrated as follows:

An I2C master initiates a write operation to the TMDS442 by generating a start condition (S) followed by the

TMDS442 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After

receiving an acknowledge from the TMDS442, the master presents the sub-address (sink port) it wants to write

consisting of one byte of data, MSB first. The TMDS442 acknowledges the byte after completion of the transfer.

Finally the master presents the data it wants to write to the register (sink port) and the TMDS442 acknowledges

the byte. The I2C master then terminates the write operation by generating a stop condition (P). Note that the

TMDS442 does not support multi-byte transfers. To write to both sink ports – or registers - this procedure must

be repeated for each register one series at a time (i.e. repeat steps 1 through 8 for each sink port).

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