TMP112 datasheet(18/46 Pages) TI2

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7.3.2 Serial Interface

The TMP112-Q1/TMP112D-Q1 device operates as a target device only on the I2C, SMBus and two-wire

interface-compatible bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL.

The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects

of input spikes and bus noise. The TMP112-Q1/TMP112D-Q1 device supports the transmission protocol for both

fast (1kHz to 400kHz) and high-speed (1kHz to 2.85MHz) modes. All data bytes are transmitted MSB first.

7.3.2.1 Bus Overview

The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets.

The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access,

and generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high-

to low-logic level when the SCL pin is high. All targets on the bus shift in the target address byte on the rising

edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock

pulse, the target being addressed responds to the controller by generating an acknowledge and pulling the SDA

pin low.

A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data

transfer the SDA pin must remain stable when the SCL pin is high, because any change in the SDA pin when the

SCL pin is high is interpreted as a START or STOP signal.

When all data have been transferred, the controller generates a STOP condition indicated by pulling the SDA pin

from low to high when the SCL pin is high.

7.3.2.2 Serial Bus Address

To communicate with the TMP112-Q1/TMP112D-Q1 device, the controller must first address target devices

through a target-address byte. The target-address byte consists of seven address bits and a direction bit

indicating the intent of executing a read or write operation.

The TMP112-Q1/TMP112D-Q1 device features an address pin to allow up to four devices to be addressed on a

single bus. Table 7-4 lists the pin logic levels used to properly connect up to four devices.

Table 7-4. Address and Alert Variant Device Target Address

DEVICE ORDERABLE

ADD0 PIN CONNECTION

DEVICE I2C BUS

ADDRESS

DEVICE I2C BUS

ADDRESS (Hex)

Address Variant Only

(X2SON-5 package)

TMP112D-Q1

GND

1000000

40h

V+

1000001

41h

SDA

1000010

42h

SCL

1000011

43h

Address and Alert

Variant

(SOT563-6 package)

TMP112-Q1

TMP112D-Q1

GND

1001000

48h

V+

1001001

49h

SDA

1001010

4Ah

SCL

1001011

4Bh

7.3.2.3 Writing and Reading Operation

Accessing a particular register on the TMP112-Q1/TMP112D-Q1 device is accomplished by writing the

appropriate value to the pointer register. The value for the pointer register is the first byte transferred after

the target address byte with the R/W bit low. Every write operation to the TMP112-Q1/TMP112D-Q1 device

requires a value for the pointer register (see Figure 7-4).

When reading from the TMP112-Q1/TMP112D-Q1 device, the last value stored in the pointer register by a write

operation is used to determine which register is read by a read operation. To change the register pointer for a

read operation, a new value must be written to the pointer register. This action is accomplished by issuing a

target-address byte with the R/W bit low, followed by the pointer register byte. No additional data are required.

TMP112-Q1, TMP112D-Q1

SLOS887G – SEPTEMBER 2014 – REVISED MAY 2025

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