TMP112 datasheet(20/46 Pages) TI2

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2.85MHz. After the Hs-mode controller code has been issued, the controller transmits a two-wire target address

to initiate a data-transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on

the bus. Upon receiving the STOP condition, the TMP112-Q1/TMP112D-Q1 device switches the input and output

filters back to fast-mode operation.

7.3.2.8 Timeout Function

The TMP112-Q1/TMP112D-Q1 device resets the serial interface if the SCL pin is held low for 30ms (typical)

between a start and stop condition. The TMP112-Q1/TMP112D-Q1 releases the SDA line if the SCL pin is pulled

low and waits for a start condition from the host controller. To avoid activating the timeout function, maintain a

communication speed of at least 1kHz for SCL operating frequency.

7.3.2.9 Timing Diagrams

The TMP112-Q1/TMP112D-Q1 device is two-wire, SMBus and I2C interface-compatible. Figure 7-4 to Figure 7-6

illustrate the various operations on the TMP112-Q1/TMP112D-Q1 device. Parameters for Figure 6-1 are listed in

the Timing Requirements table. The bus definitions are defined as follows:

Bus Idle:

Both SDA and SCL lines remain high.

Start Data

Transfer:

A change in the state of the SDA line, from high to low, when the SCL line is high, defines a

START condition. Each data transfer is initiated with a START condition.

Stop Data

Transfer:

A change in the state of the SDA line from low to high when the SCL line is high defines

a STOP condition. Each data transfer is terminated with a repeated START or STOP

condition.

Data Transfer:

The number of data bytes transferred between a START and a STOP condition is not

limited and is determined by the controller device. Using the TMP112-Q1/TMP112D-Q1

device for single byte updates is also possible. To update only the most-significant (MS)

byte, terminate the communication by issuing a START or STOP communication on the

bus.

Acknowledge:

Each receiving device, when addressed, is obliged to generate an acknowledge bit. A

device that acknowledges must pull down the SDA line during the acknowledge clock pulse

in such a way that the SDA line is stable low during the high period of the acknowledge

clock pulse. Setup and hold times must be taken into account. On a controller receive,

the termination of the data transfer can be signaled by the controller generating a not-

acknowledge (1) on the last byte that has been transmitted by the target.

7.3.2.9.1 Two-Wire Timing Diagrams

See the Timing Requirements table for timing specifications.

TMP112-Q1, TMP112D-Q1

SLOS887G – SEPTEMBER 2014 – REVISED MAY 2025

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