TMP112 datasheet(25/46 Pages) TI2

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reset values of the configuration register. For compatibility, the first byte corresponds to the configuration register

in the TMP75 and TMP275 devices. All registers are updated byte by byte.

Table 7-9. Configuration and Power-Up and Reset Formats

BYTE

POL

CR1

CR0

7.5.3.1 Shutdown Mode (SD)

The shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial

interface which reduces current consumption to typically less than 0.5μA for TMP112-Q1 and 0.15μA for

TMP112D-Q1. Shutdown mode is enabled when the SD bit is set to 1. When this bit is set to 1 the device

shuts down when current conversion is completed. When the SD bit is set to 0 the device maintains a continuous

conversion state.

7.5.3.2 Thermostat Mode (TM)

The Thermostat mode bit indicates to the device whether to operate in comparator mode (TM = 0 shown in

Figure 7-9) or interrupt mode (TM = 1 shown in Figure 7-10). For more information on comparator and interrupt

modes, see the High- and Low-Limit Registers section.

7.5.3.3 Polarity (POL)

The polarity bit allows the user to adjust the polarity of the ALERT pin/flag output. If the POL bit is set to 0

(default), the ALERT pin/flag becomes active low . When the POL bit is set to 1, the ALERT pin/flag becomes

active high and the state of the ALERT pin/flag is inverted. The operation of the ALERT pin/flag in various modes

is shown in Figure 7-9 and Figure 7-10.

THigh_Limit

TLow_Limit

Temperature

Conversions

ALERT pin/ ag

Polarity = 0b

ALERT pin/ ag

Polarity = 1b

2C Read

Temperature

Figure 7-9. Comparator Mode

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TMP112-Q1, TMP112D-Q1

SLOS887G – SEPTEMBER 2014 – REVISED MAY 2025

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TMP112 Datasheet(PDF) 25 Page - Texas Instruments