TMP112 datasheet(19/46 Pages) TI2

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The controller can then generate a START condition and send the target address byte with the R/W bit high

to initiate the read command. See Figure 7-5 for details of this sequence. If repeated reads from the same

TMP112D-Q1 device retains the pointer register value until the value is changed by the next write operation.

7.3.2.4 Target Mode Operation

The TMP112-Q1/TMP112D-Q1 device can operate as a target receiver or target transmitter. As a target device,

the TMP112-Q1/TMP112D-Q1 device never drives the SCL line.

7.3.2.4.1 Target Receiver Mode

The first byte transmitted by the controller is the target address with the R/W bit low. The TMP112-Q1/TMP112D-

Q1 device then acknowledges reception of a valid address. The next byte transmitted by the controller is the

pointer register. The TMP112-Q1/TMP112D-Q1 device then acknowledges reception of the pointer register byte.

The next byte or bytes are written to the register addressed by the pointer register. The TMP112-Q1/TMP112D-

Q1 device acknowledges reception of each data byte. The controller can terminate data transfer by generating a

START or STOP condition.

7.3.2.4.2 Target Transmitter Mode

The first byte transmitted by the controller is the target address with the R/W bit high. The target acknowledges

reception of a valid target address. The next byte is transmitted by the target and is the most significant byte of

the register indicated by the pointer register. The controller acknowledges reception of the data byte. The next

byte transmitted by the target is the least significant byte. The controller acknowledges reception of the data

byte. The controller can terminate data transfer by generating a not-acknowledge on reception of any data byte

or by generating a START or STOP condition.

7.3.2.5 SMBus Alert Function

The TMP112-Q1/TMP112D-Q1 device supports the SMBus alert function. When the TMP112-Q1/TMP112D-Q1

device operates in interrupt mode (TM = 1), the ALERT pin can be connected as an SMBus alert signal. When

a controller senses that an alert condition is present on the alert line, the controller sends an SMBus ALERT

command (0001 1001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus ALERT

command and responds by returning the target address on the SDA line. The eighth bit (LSB) of the target

address byte indicates if the alert condition is caused by the temperature exceeding T(HIGH) or falling below

T(LOW). The LSB is high if the temperature is greater than T(HIGH), or low if the temperature is less than T(LOW).

See Figure 7-6 for details of this sequence.

If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the target address

portion of the SMBus ALERT command determines which device clears the alert status of that device. The

device with the lowest two-wire address wins the arbitration. If the TMP112-Q1/TMP112D-Q1 device wins the

arbitration, the TMP112-Q1/TMP112D-Q1 ALERT pin becomes inactive at the completion of the SMBus ALERT

command. If the TMP112-Q1/TMP112D-Q1 device loses the arbitration, the TMP112-Q1/TMP112D-Q1 ALERT

pin remains active.

7.3.2.6 General Call

The TMP112-Q1/TMP112D-Q1 device responds to a two-wire general-call address (0000 000) if the eighth bit

is 0. The device acknowledges the general-call address and responds to commands in the second byte. If the

second byte is 0000 0110, the TMP112-Q1/TMP112D-Q1 internal registers are reset to power-up values. The

TMP112-Q1/TMP112D-Q1 device does not support the general-address acquire command.

7.3.2.7 High-Speed (Hs) Mode

For the two-wire bus to operate at frequencies above 400kHz, the controller device must issue an Hs-mode

controller code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speed operation.

The TMP112-Q1/TMP112D-Q1 device does not acknowledge this byte, but switches the input filters on the SDA

and SCL pins and the output filters on the SDA pin to operate in Hs-mode thus allowing transfers at up to

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TMP112-Q1, TMP112D-Q1

SLOS887G – SEPTEMBER 2014 – REVISED MAY 2025

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