TPL0102 datasheet(35/48 Pages) TI2

35 / 48 page

VDD

GND

SCL

SDA

VSS

TPL0102

Via to GND Plane

Via to VDD Power Plane

Via to VSS Power Plane

TPL0102

www.ti.com

SLIS134C – MARCH 2011 – REVISED SEPTEMBER 2015

Product Folder Links: TPL0102

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10 Layout

10.1 Layout Guidelines

To ensure reliability of the device, please follow common printed-circuit board layout guidelines.

•

Leads to the input should be as direct as possible with a minimum conductor length.

•

The ground path should have low resistance and low inductance.

•

Short trace-lengths should be used to avoid excessive loading.

•

It is common to have a dedicated ground plane on an inner layer of the board.

•

Terminals that are connected to ground should have a low-impedance path to the ground plane in the form of

wide polygon pours and multiple vias.

•

Bypass capacitors should be used on power supplies and should be placed as close as possible to the VDD

and VSS pins.

•

Apply low equivalent series resistance 0.1 µF to 10 µF tantalum or electrolytic capacitors at the supplies to

minimize transient disturbances and to filter low frequency ripple.

•

To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCL and SDA) should be a

short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper

weight).

10.2 Layout Example

Figure 37. TPL0102 Layout Example

TPL0102 Datasheet(PDF) 35 Page - Texas Instruments