TPS23754PWPR datasheet(21/48 Pages) TI2

21 / 48 page

Idle

Detect

Class

Mark

Class

Mark

Class

Between

Ranges

Between

Ranges

Operating

T2P

open-drain

Operating

T2P low

Mark

Reset

Between

Ranges

UVLO

Rising

UVLO

Falling

UVLO

Rising

UVLO

Falling

TYPE2PSE

HardwareClass

Class

Mark

Reset

TYPE1PSE

HardwareClass

TPS23754, TPS23754-1, TPS23756

www.ti.com

SLVS885I – OCTOBER 2008 – REVISED DECEMBER 2017

Product Folder Links: TPS23754 TPS23754-1 TPS23756

Submit Documentation Feedback

Figure 23. Two-Event Class Internal States

7.4.1.5 Inrush and Start-Up

802.3at has a start-up current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2

PSE limits output current to from 400 mA to 450 mA for up to 75 ms after power up (applying 48 V to the PI) to

mirror type 1 PSE functionality. The type 2 PSE supports higher output current after 75 ms. The TPS23754

implements a 140-mA inrush current, which is compatible with all PSE types. A high-power PD must control its

converter start-up peak and operational currents drawn to less than 400 mA for 80 ms. The TPS23754 device's

internal soft-start permits control of the converter start-up; however, the application circuits must assure that their

power draw does not cause the PD to exceed the current/time limitation. This requirement implicitly requires

some form of powering down sections of the application circuits. T2P becomes valid within tT2P after switching

starts, or if an adapter is plugged in while the PD is operating from a PSE.

7.4.1.6 Maintain Power Signature

The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating

voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (or a 10-mA pulsed current for at

least 75 ms every 325 ms) and an AC impedance lower than 26.3 k

Ω in parallel with 0.05 μF. The AC impedance

is usually accomplished by the minimum operating CIN requirement of 5 μF. When either APD or DEN is used to

force the hotswap switch off, the DC MPS will not be met. A PSE that monitors the DC MPS will remove power

from the PD when this occurs. A PSE that monitors only the AC MPS may remove power from the PD.

7.4.1.7 Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full

voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and

classification. The converter circuits discharge CIN, CVC, and CVB while the PD is unpowered. Thus VVDD-VRTN will

be a small voltage just after full voltage is applied to the PD, as seen in Figure 22. The PSE drives the PI voltage

to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon

threshold (VUVLO-R, about 35 V) with RTN high, the TPS23754 device enables the hotswap MOSFET with an

approximately 140-mA (inrush) current limit as seen in Figure 24. Converter switching is disabled while CIN

charges and VRTN falls from VVDD to nearly VVSS, however the converter start-up circuit is allowed to charge CVC

(the bootstrap start-up capacitor). Additional loading applied between VVDD and VRTN during the inrush state may

prevent successful PD and subsequent converter start-up. Converter switching is allowed if the PD is not in

inrush, OTSD is not active, and the VC UVLO permits it. Once the inrush current falls about 10% less than the

inrush current limit, the PD current limit switches to the operational level (about 970 mA). Continuing the start-up

sequence shown in Figure 24, VVC continues to rise until the start-up threshold (VCUV, about 15 V or about 9 V) is

exceeded, turning the start-up source off and enabling switching. The VB regulator is always active, powering the

TPS23754PWPR Datasheet(PDF) 21 Page - Texas Instruments

TPS23754PWPR Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL