TPS23754PWPR datasheet(30/48 Pages) TI2

30 / 48 page

FRS

17250

(k ) =

= 69

(kHz)

250

(

)

RPPD

PPD1

PPD2

24 V

1.1

)

= 19.6 mW

+ R

3.01 k

+ 32.4 k

(

)

(

)

PPDEN

PPDH

ADPTR_OFF

PPDEN

PPDH

PPD1

PPD

PPD2

= V

+ R

= 14.75 V

PPDEN

ADPTR_ON

PPDEN

PPD1

PPD

PPD2

= V

+ R

= 18.4 V

ADPTR_ON

PPDEN

PPD1

PPDEN

PPD

PPD2

18 V 1.55 V

= 31.64 k

1.55 V

5 A

3.01 k

ö æ

÷ ç

+ m

TPS23754, TPS23754-1, TPS23756

SLVS885I – OCTOBER 2008 – REVISED DECEMBER 2017

www.ti.com

Product Folder Links: TPS23754 TPS23754-1 TPS23756

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Typical Application (continued)

4. Calculate RPPD1.

b. Choose RPPD1 = 32.4 kΩ.

5. Check PPD turnon and PPD turnoff voltages.

c. Voltages look acceptable.

6. Check PPD resistor power consumption.

b. Power is acceptable, but resistor values could be increased to reduce the power loss.

The PPD pin can also be used to modify the internal MOSFET UVLO for use with a lower output voltage

PSE (within certain limits). Connect the RPPD1 and RPPD2 dividers directly between VDD and VSS with

the midpoint connected to PPD. For this case and to allow classification, target the minimum PSE OFF

voltage (VADPTR_OFF) > VCU_OFF = 23 V. Then follow the procedure outlined above to select RPPD1, RPPD2,

and determine the PSE ON (VADPTR_ON) and PSE OFF (VADPTR_OFF) voltages ensuring that PSE OFF >

23 V. Lastly, because the RPPD1 and RPPD2 divider is in parallel with RDEN during detection, RDEN must be

increased such that the equivalent detection resistance is 25 kΩ nominal.

8.2.2.12 Setting Frequency (RFRS) and Synchronization

The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. The frequency may be

set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization

at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the

available on-time. As an example:

1. Assume a desired switching frequency (fSW) of 250 kHz.

2. Compute RFRS:

b. Select 69.8 k

Ω.

The TPS23754 device may be synchronized to an external clock to eliminate beat frequencies from a sampled

system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished

by applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 30. RFRS should be chosen so

that the maximum free-running frequency is just below the desired synchronization frequency. The

synchronization pulse terminates the potential on-time period, and the off-time period does not begin until the

pulse terminates. The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns

(above 2.5 V) and rise and fall times less than 10 ns. The FRS node should be protected from noise because it is

high-impedance. An RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

TPS23754PWPR Datasheet(PDF) 30 Page - Texas Instruments

TPS23754PWPR Datasheet(HTML) 30 Page - Texas Instruments

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