TPS23754PWPR datasheet(29/48 Pages) TI2

29 / 48 page

VC1

ARTN

BiasWinding

(ns)

100

(k ) =

= 50

TPS23754, TPS23754-1, TPS23756

www.ti.com

SLVS885I – OCTOBER 2008 – REVISED DECEMBER 2017

Product Folder Links: TPS23754 TPS23754-1 TPS23756

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Typical Application (continued)

8.2.2.6 Dead Time Resistor, RDT

The required dead-time period depends on the specific topology and parasitics. The easiest technique to obtain

the optimum timing resistor is to build the supply and tune the dead time to achieve the best efficiency after

considering all corners of operation (load, input voltage, and temperature). A good initial value is 100 ns.

Program the dead time with a resistor connected from DT to ARTN per Equation 3.

1. Choose RDT as follows assuming a tDT of 100 ns:

b. Choose RDT = 49.9 kΩ

8.2.2.7 Switching Transformer Considerations and RVC

Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection. Leading-

edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with

output voltage. Some method of controlling this is usually required. This may be as simple as a series resistor, or

an R-C filter in front of DVC1. Good transformer bias-to-output-winding coupling results in reduced overshoot and

better voltage tracking.

RVC as shown in Figure 29 helps to reduce peak charging from the bias winding. This becomes especially

important when tuning hiccup mode operation during output overload. Typical values for RVC will be from 10 Ω to

100

Ω.

Figure 29. RVC Usage

8.2.2.8 Special Switching MOSFET Considerations

Special care must be used in selecting the converter switching MOSFET. The TPS23756 minimum switching

MOSFET VGATE is about 5.5 V, which is due to the VC lower threshold. This will occur during an output overload,

or toward the end of a (failed) bootstrap start-up. The MOSFET must be able to carry the anticipated peak fault

current at this gate voltage.

8.2.2.9 Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations

assume that the TPS23754 device is the only heat source contributing to the PCB temperature rise. It is possible

for a normally operating TPS23754 device to experience an OTSD event if it is excessively heated by a nearby

device.

8.2.2.10 APD Pin Divider Network, RAPD1, RAPD2

The APD pin can be used to disable the TPS23754 device internal hotswap MOSFET giving the adapter source

priority over the PoE source. An example calculation is provided, see SLVA306.

8.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2

The PPD pin can be used to override the internal hotswap MOSFET UVLO (VUVLO_R and VUVLO_H) when using

low voltage adapters connected between VDD and VSS. The PPD pin has an internal 5-μA pulldown current

source. As an example, consider the choice of RPPD1 and RPPD2, for a 24-V adapter.

1. Select the start-up voltage, VADPTR-ON approximately 75% of nominal for a 24-V adapter. Assuming that the

adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.

2. Choose VADPTR-ON = 24 V × 0.75 = 18 V.

3. Choose RPPD2 = 3.01 kΩ.

TPS23754PWPR Datasheet(PDF) 29 Page - Texas Instruments

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