TPS23754PWPR datasheet(22/48 Pages) TI2

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t-Time-10ms/div

IPI

V DD-RTN

V C-RTN

Inrush

VOUT

PIPowered

Switchingstarts

T2P @output

5V/div

200mA/div

10V/div

2V/div

50V/div

TPS23754, TPS23754-1, TPS23756

SLVS885I – OCTOBER 2008 – REVISED DECEMBER 2017

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internal converter circuits as VVC rises. There is a slight delay between the removal of charge current and the

start of switching as the soft-start ramp sweeps above the VZDC threshold. VVC falls as it powers both the internal

circuits and the switching MOSFET gates. If the converter control bias output rises to support VVC before it falls

to VCUV – VCUVH (about 8.5 V or about 5.5 V), a successful start-up occurs. T2P in Figure 22 (Figure 27, VT2P-OUT)

becomes active within tT2P from the start of switching, indicating that a type 2 PSE or an adapter is plugged in.

Figure 24. Power Up and Start

If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, about 30.5 V), the hotswap MOSFET is turned

off, but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH,

about 8.5 V or about 5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL <

VZDC, about 1.5 V), or the converter is in thermal shutdown.

7.4.1.8 PD Hotswap Operation

IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current

versus time template with specified minimum and maximum sourcing boundaries. The peak output current may

be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more

important than it was in IEEE 802.3-2008.

The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and

deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with VRTN-

VVSS rising as a result. If VRTN rises above about 12 V for longer than about 400 μs, the current limit reverts to

the inrush value, and turns the converter off. The 400 μs deglitch feature prevents momentary transients from

causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 25

shows an example of recovery from a 16 V PSE rising voltage step. The hotswap MOSFET goes into current

limit, overshooting to a relatively low current, recovers to about 950-mA full current limit, and charges the input

capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VVSS was

less than 12 V after the 400 μs deglitch.

TPS23754PWPR Datasheet(PDF) 22 Page - Texas Instruments

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