Thermal

Shutdown

Softstart

Under

Voltage

Lockout

direct control

&

compensation

PG

EN

VOS

REF

Power

Good

MODE

FB

ramp

minimum

on-timer

DCS-CONTROL

TM

Gate

Driver

Control

Logic

Low Side

N-MOS

High Side

N-MOS

VIN

SW

GND

Snooze Mode

comparator

error

amplifier

Active

Output

Discharge

50

Copyright © 2016, Texas Instruments Incorporated

9

TPS62080, TPS62080A, TPS62081, TPS62082

www.ti.com

SLVSAE8F – SEPTEMBER 2011 – REVISED NOVEMBER 2016

Product Folder Links: TPS62080 TPS62080A TPS62081 TPS62082

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Copyright © 2011–2016, Texas Instruments Incorporated

Functional Block Diagrams (continued)

Figure 6. Functional Block Diagram (Fixed Output Voltage Version)

8.3 Feature Description

8.3.1 Power Good

The TPS6208x has a power good output which goes low when the output voltage is below its nominal value. The

power good is high impedance once the output is above 95% of the regulated voltage, and is driven to low once

the output voltage falls below typically 90% of the regulated voltage. The PG pin is an open drain output and can

sink up to 0.5 mA. The power good output requires a pull-up resistor. When the device is off due to disable,

UVLO or thermal shutdown, the PG pin is high impedance (see Table 1). The PG signal can be used for

sequencing of multiple rails by connecting to the EN pin of other converters. Leave the PG pin unconnected

when not used.

space

Table 1. Power Good Pin Logic Table

Device Information

PG Logic Status

High Z

Low

Enable (EN=High)

VFB ≥ VPG

√

VFB ≤ VPG

√

Shutdown (EN=Low)

√

UVLO

0.7V < VIN < VUVLO

√

Thermal Shutdown

TJ > TJSD

√

Power Supply Removal

VIN < 0.7V

√