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DAC38RF80 Datasheet(PDF) 36 Page - Texas Instruments |
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DAC38RF80 Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 160 page  7.3 Feature Description 7.3.1 SerDes Inputs The DAC38RFxx RX [0..7]+/- differential inputs are each internally terminated to a common point through 50 Ω, as shown in Figure 7-7. 0.7V 0.25V 50pF 50O 50O TERM =100 TERM =001 TERM =101 Level Shift RXP RXN To Equalizer & Samplers Figure 7-7. Serial Lane Input Termination Common mode termination is through a 50 pF capacitor to GND. The common mode voltage and termination of the differential signal can be controlled in a number of ways to suit a variety of applications through field TERM in register SRDS_CFG2 (8.5.87), as described in Table 7-1. Note AC coupling is recommended for JESD204B compliance. Table 7-1. Receiver Termination Selection TERM EFFECT 000 Reserved 001 Common point set to 0.7 V. This configuration is for AC coupled systems. The transmitter has no effect on the receiver common mode, which is set to optimize the input sensitivity of the receiver. Note: this mode is not compatible with JESD204B. 01x Reserved 100 Common point set to GND. This configuration is for applications that require a 0 V common mode. 101 Common point set to 0.25 V. This configuration is for applications that require a low common mode. 110 Reserved 111 Common point floating. This configuration is for DC coupled systems in which the common mode voltage is set by the attached transmit link partner to 0 and 0.6 V. Note: this mode is not compatible with JESD204B Input data is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. The polarity of RX+ and RX- can be inverted by setting the bit of the corresponding lane in field INVPAIR in register SRDS_POL (8.5.88) to “1”. This can potentially simplify PCB layout and improve signal integrity by avoiding the need to swap over the differential signal traces. Due to processing effects, the devices in the RX+ and RX- differential sense amplifiers will not be perfectly matched and there will be some offset in switching threshold. The DAC38RFxx contains circuitry to detect and correct for this offset. This feature can be enabled by setting ENOC in register SRDS_CFG1 (8.5.86) to “1”. It is anticipated the most users will enable this feature. During the compensation process, LOOPBACK in register SRDS_CFG1 (8.5.86) must be set to “00”. DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023 www.ti.com 36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 |
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