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DAC38RF80 Datasheet(PDF) 7 Page - Texas Instruments |
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DAC38RF80 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 160 page  A B C D E F G H J K L M 12 11 10 9 8 7 6 5 4 3 2 1 Not to scale DACCLKSE VSSCLK AGND AGND VOUT2 AGND VDDOUT18 VDDOUT18 AGND VOUT1 AGND AGND VSSCLK VSSCLK AGND AGND AGND VDDA1 VDDA18 VDDA18 VDDA1 AGND AGND AGND DACCLK+ VDDAPLL18 EXTIO VEE18N VEE18N VSSCLK VDDL2_1 VDDL2_1 VSSCLK VEE18N VEE18N SDIO DACCLK- VDDAPLL18 RBIAS VDDAVCO18 VDDAVCO18 VSSCLK VDDCLK1 VDDCLK1 VSSCLK RESET SCLK SDO VSSCLK VSSCLK ATEST VDDPLL1 VDDPLL1 VSSCLK VDDL1_1 VDDL1_1 VSSCLK ALARM SLEEP SDEN CLKTX+ VDDTX18 SYNC1+ VDDDIG1 DGND VDDE1 DGND VDDE1 DGND GPIO1 GPO0 GPI1 CLKTX- VDDTX1 SYNC1- DGND VDDDIG1 DGND VDDE1 DGND VDDE1 TXENABLE GPI0 DGND VDDDIG1 VDDDIG1 VDDDIG1 VDDDIG1 VDDDIG1 VDDDIG1 VDDDIG1 VDDIO18 TRST TMS DGND RX3+ SYSREF- VDDS18 SYNC0+ VSENSE VDDDIG1 VDDDIG1 VDDDIG1 TDI TDO TCLK DGND RX3- SYSREF+ VDDS18 SYNC0- IFORCE VDDDIG1 AMUX1 AMUX0 VDDT1 VDDT1 TESTMODE DGND RX2- DGND DGND DGND DGND DGND DGND DGND VDDR18 VDDR18 DGND DGND RX2+ RX7+ RX7- RX6- RX6+ RX5+ RX5- RX4- RX4+ RX0+ RX0- RX1- RX1+ Figure 5-2. DAC38RF80, DAC38RF84, DAC38RF90 AAV Package 144-Pin (FCBGA) 144-Pin FCBGA Top View Pin Functions - DAC38RF80, DAC38RF90, DAC38RF84 PIN I/O DESCRIPTION NAME NO. AGND C11, C12, D11, E11, F12, J12, K11, L11, M11, M12, D12, L12 - Analog ground. ALARM K8 O CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high through RESET_CONFIG alm_out_pol control bit. AMUX0 G3 O Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating. AMUX1 F3 O Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating. www.ti.com DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 |
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