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DM505 Datasheet(PDF) 160 Page - Texas Instruments

Part # DM505
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505 Datasheet(HTML) 160 Page - Texas Instruments

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DM505
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com
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Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Table 5-53. Timing Requirements for McASP2 (1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
0.5R - 3
(3)
ns
IOSET1 only,
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
0.38R
(3)
ns
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
ACLKR/X int
18.5
ns
IOSET1 (vout1_*):
ACLKR/X ext in
IOSET1 (vout1_*):
ACLKR/X ext out
4
ns
IOSET2 (gpmc_*):
ACLKR/X ext in
IOSET2 (gpmc_*):
ACLKR/X ext out
3
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
ACLKR/X int
0.5
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
7
tsu(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
ACLKR/X int
18.5
ns
IOSET1 (vout1_*):
ACLKR/X ext in
IOSET1 (vout1_*):
ACLKR/X ext out
12
ns
IOSET2 (gpmc_*):
ACLKR/X ext in
IOSET2 (gpmc_*):
ACLKR/X ext out
3
ns
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
0.5
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
Table 5-54. Timing Requirements for McASP3 (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
1
tc(AHCLKX)
Cycle time, AHCLKX
20
ns
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
ns
3
tc(ACLKRX)
Cycle time, ACLKR/X
20
ns
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5R - 3
ns
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
ACLKR/X int
18.2
ns
ACLKR/X ext in
ACLKR/X ext out
4
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
ACLKR/X int
0.5
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
tsu(AXR-ACLK)
Setup time, AXR input valid before ACLKX
ACLKX int (ASYNC=0)
18.2
ns
ACLKR/X ext in
ACLKR/X ext out
12
ns



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