DM505 datasheet(161/295 Pages) TI2

161 / 295 page

A30 A31

B30 B31 C0 C1

C2 C3

C31

AHCLKX (Falling Edge Polarity)

AHCLKX (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data In/Receive)

ACLKR/X (CLKRP = CLKXP = 0)(A)

ACLKR/X (CLKRP = CLKXP = 1)(B)

SPRS91v_McASP_01

161

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

Submit Documentation Feedback

Specifications

Table 5-54. Timing Requirements for McASP3 (1) (continued)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

th(ACLK-AXR)

Hold time, AXR input valid after ACLKX

ACLKX int (ASYNC=0)

0.5

ACLKR/X ext in

ACLKR/X ext out

0.5

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2) P = AHCLKX period in ns.

(3) R = ACLKR/X period in ns.

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 5-49. McASP Input Timing

DM505 Datasheet(PDF) 161 Page - Texas Instruments

DM505 Datasheet(HTML) 161 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL