DM505 datasheet(197/295 Pages) TI2

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DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

•

Video Encoder (VENC) with 10-bit standard definition video DAC (SD_DAC).

For more information, see section Video Encoder in chapter Display Subsystem of the device TRM.

DSS provides two interfaces to L3_MAIN interconnect

•

One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master to

read/write data from/to device system memory.

•

One 32-bit slave port. Used for registers configuration. It is further connected internally to DISPC and

VENC modules.

For more information, see chapter Display Subsystem of the device TRM.

6.10.3 ADC

The analog-to-digital converter (ADC) module is a successive-approximation-register (SAR) general-

purpose analog-to-digital converter.

The main features of the ADC include:

•

10-bit data.

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8 general-purpose ADC channels.

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750 KSPS at 13.5-MHz ADC_CLK.

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Programmable FSM sequencer.

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Support interrupts and status, with masking.

For more information, see chapter ADC of the device TRM.

6.10.4 ISS

The imaging subsystem (ISS) deals with the processing of the pixel data coming from an external image

sensor or data from memory (image format encoding and decoding can be done to and from memory).

With its subparts, such as interfaces and interconnects, image signal processor (ISP), and still image

coprocessor (SIMCOP), the ISS is a key component for the following applications:

•

Rear View Camera

•

Front View Stereo Camera

•

Surround View Camera

The ISS offers the following features:

•

ISS interfaces:

–

Camera Adapter Layer (CAL_A) module, which serves as sensor capture interface supporting

MIPI® CSI-2 protocol via external MIPI D-PHY module (CSI2_PHY1), and in addition provides write

DMA capability

–

CAL_B module, serving as internal read DMA engine, without direct sensor capture interface

capability

–

Parallel interface (CPI) (16 bits wide, with up to 212.8 MPix/s throughput, and supporting BT656,

SYNC modes)

–

LVDS receiver

–

128-bit-wide data interface to L3_MAIN interconnect

For more information, see chapter Imaging Subsystem of the device TRM.

6.10.5 Timers

The device includes several types of timers used by the system software, including eight general-purpose

(GP) timers, and a 32-kHz synchronized timer (COUNTER_32K).

6.10.5.1 General-Purpose Timers

The device has eight GP timers: TIMER1 through TIMER8.

DM505 Datasheet(PDF) 197 Page - Texas Instruments

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