DM505 datasheet(193/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

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Dual Cortex-M4 image processing unit (IPU) subsystems – IPU1 and IPU2

The Spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient

way to perform a lock operation of a device resource using a single read-access, avoiding the need of

a readmodify- write bus transfer that the programmable cores are not capable of.

For more information, see chapter Spinlock of the device TRM.

6.8

Interrupt Controller

The device has a large number of interrupts to service the needs of its many peripherals and subsystems.

The DSP (x2), and IPU, and EVE subsystems are capable of servicing these interrupts via their integrated

interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller

Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor

interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device

TRM.

C66x DSP Subsystem Interrupt Controller (DSPx_INTC, where x = 1, 2)

There are two Digital Signal Processing (DSP) subsystems in the device - DSP1, and DSP2. Each DSP

subsystem integrates an interrupt controller - DSPx_INTC, which interfaces the system events to the C66x

core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized interrupts

presented to the C66x CPU.

For detailed information about this module, see chapter DSP Subsystems of the Device TRM.

Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPU_Cx_INTC, where x = 1, 2)

There is one Image Processing Unit (IPU) subsystem in the device. The IPU subsystem integrates two

Arm® Cortex-M4 cores.

A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping

is the same for the two cores to facilitate parallel processing. The NVIC supports:

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96 external interrupts (in addition to 16 Cortex-M4 internal interrupts), which are dynamically prioritized

with 16 levels of priority defined for each core

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Low-latency exception and interrupt handling

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Prioritization and handling of exceptions

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Control of the local power management

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Debug accesses to the processor core

For detailed information about this module, refer to Arm Cortex-M4 Technical Reference Manual (available

at infocenter.arm.com/help/index.jsp).

EVE Subsystem Interrupt Controller (EVE_INTC)

There is one Embedded Video Engine (EVE) subsystems in the device. The EVE subsystem integrates an

interrupt controller - EVE_INTC, which handles incoming interrupts, merging them with internal interrupt

sources to drive ARP32's interrupt inputs. It also allows ARP32 to generate outgoing interrupts or events

to synchronize with other system processors and EDMA.

The EVE_INTC supports up to 32 active-high level interrupt inputs. Its architecture allows both hardware

and software prioritization.

For detailed information about this module, see chapter Embedded Vision Engine of the Device TRM.

6.9

EDMA

The enhanced direct memory access module, also called EDMA, performs high-performance data

transfers between two slave points, memories and peripheral devices without microprocessor unit (MPU)

or digital signal processor (DSP) support during transfer. EDMA transfer is programmed through a logical

EDMA channel, which allows the transfer to be optimally tailored to the requirements of the application.

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