DM505 datasheet(192/295 Pages) TI2

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192

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

•

ECC Diagnostics Configuration:

–

Counters for single error correction (SEC), double error detection (DED) and address error events

(AEE)

–

Programmable threshold registers for exeptions associated with SEC, DED and AEE counters

–

Configuration registers and ECC status accessible through L4 interconnect

•

Circular buffer for sliced based VIP frame transfers:

–

Up to 12 programmable circular buffers mapped with unique virtual frame addresses

–

On the fly (with no additional latency) address translation from virtual to OCMC circular buffer

memory space

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Virtual frame size up to 8 MiB and circular buffer size up to 1 MiB

–

Error handling and reporting of illegal CBUF addressing

–

Underflow and Overflow status reporting and error handling

–

Last access read/write address history

•

Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events

The OCM controller does not have a memory protection logic and does not support endianism conversion.

For more information, see section On-Chip Memory (OCM) Subsystem in chapter Memory Subsystem of

the device TRM.

6.7

Interprocessor Communication

6.7.1

Mailbox

Communication between the on-chip processors of the device uses a queued mailbox-interrupt

mechanism.

The queued mailbox-interrupt mechanism allows the software to establish a communication channel

between two processors through a set of registers and associated interrupt signals by sending and

receiving messages (mailboxes).

The device implements the following mailbox types:

•

System mailbox:

–

Number of instances: 2

–

Used for communication between: DSP1, DSP2, IPU subsystems

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Reference name: MAILBOX1, MAILBOX2

Each mailbox module supports the following features:

•

Parameters configurable at design time

–

Number of users

–

Number of mailbox message queues

–

Number of messages (FIFO depth) for each message queue

•

32-bit message width

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Message reception and queue-not-full notification using interrupts

•

Support of 16-/32-bit addressing scheme

•

Power management support

For more information, see chapter Mailbox of the device TRM.

6.7.2

Spinlock

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple

processors in the device:

•

Digital signal processor (DSP) subsystems – DSP1 and DSP2

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