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DM505 Datasheet(PDF) 190 Page - Texas Instruments |
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DM505 Datasheet(HTML) 190 Page - Texas Instruments |
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190 / 295 page  190 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated • OCD calibration for DDR2 • CAS Read Latency of 2 and CAS Write Latency of 1 for DDR2 • DLL disabling from EMIF side For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem of the device TRM. 6.6.2 GPMC The General Purpose Memory Controller (GPMC) is an external memory controller of the device. Its data access engine provides a flexible programming model for communication with all standard memories. The GPMC supports the following various access types: • Asynchronous read/write access • Asynchronous read page access (4, 8, and 16 Word16) • Synchronous read/write access • Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16) • Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16) • Address-data-multiplexed (AD) access • Address-address-data (AAD) multiplexed access • Little- and big-endian access The GPMC can communicate with a wide range of external devices: • External asynchronous or synchronous 8-bit wide memory or device (non burst device) • External asynchronous or synchronous 16-bit wide memory or device • External 16-bit non-multiplexed NOR flash device • External 16-bit address and data multiplexed NOR Flash device • External 8-bit and 16-bit NAND flash device • External 16-bit pseudo-SRAM (pSRAM) device The main features of the GPMC are: • 8- or 16-bit-wide data path to external memory device • Supports up to eight CS regions of programmable size and programmable base addresses in a total address space of 1 GiB • Supports transactions controlled by a firewall • On-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with 512-byte page size or greater) • Fully pipelined operation for optimal memory bandwidth use • The clock to the external memory is provided from GPMC functional clock divided by 1, 2, 3, or 4 • Supports programmable autoclock gating when no access is detected • Independent and programmable control signal timing parameters for setup and hold time on a per-chip basis. Parameters are set according to the memory device timing parameters, with a timing granularity of one GPMC functional clock cycle. • Flexible internal access time control (WAIT state) and flexible handshake mode using external WAIT pin monitoring • Support bus keeping • Support bus turnaround • Prefetch and write posting engine associated with a device DMA to achieve full performance from the NAND device with minimum effect on NOR/SRAM concurrent access |
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