DM505 datasheet(191/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory

Subsystem of the device TRM.

6.6.3

ELM

When reading from NAND flash memories, some level of error-correction is required. In the case of NAND

modules with no internal correction capability, sometimes referred to as bare NANDs, the correction

process is delegated to the memory controller.

The ELM supports the following features:

•

4, 8, and 16 bits per 512-byte block error location based on BCH algorithm

•

Eight simultaneous processing contexts

•

Page-based and continuous modes

•

Interrupt generation when error location process completes:

–

When the full page has been processed in page mode

–

For each syndrome polynomial (checksum-like information) in continuous mode

For more information, see section Error Location Module in chapter Memory Subsystem of the device

TRM.

6.6.4

OCMC

There is one on-chip memory controller (OCMC) in the device.

The OCM Controller supports the following features:

•

L3_MAIN data interface:

–

Used for maximum throughput performance

–

128-bit data bus width

–

Burst supported

•

L4 interface:

–

Used for access to configuration registers

–

32-bit data bus width

–

Only single accesses supported

–

The L4 associated OCMC clock is two times lower than the L3 associated OCMC clock

•

Error correction and detection:

–

Single error correction and dual error detection

–

9-bit Hamming error correction code (ECC) calculated on 128-bit data word which is concatenated

with memory address bits

–

Hamming distance of 4

–

Enable/Disable mode control through a dedicated register

–

Single bit error correction on a read transaction

–

Exclusion of repeated addresses from correctable error address trace history

–

ECC valid for all write transactions to an enabled region

–

Sub-128-bit writes supported via read modify write

•

ECC Error Status Reporting:

–

Trace history buffer (FIFO) with depth of 4 for corrected error address

–

Trace history buffer with depth of 4 for non correctable error address and also including double

error detection

–

Interrupt generation for correctable and uncorrectable detected errors

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