DM505 datasheet(210/295 Pages) TI2

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210

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

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System instrumentation (trace)

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Supported by a CTools System Trace Module (CT_STM), implementing MIPI System Trace

Protocol (STP) (rev 2.0)

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Real-time software trace

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System-on-chip (SoC) software instrumentation through CT_STM (STP2.0)

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OCP watchpoint (OCP_WP_NOC)

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OCP target traffic monitoring: OCP_WP_NOC can be configured to generate a trigger upon

watchpoint match (that is, when target transaction attributes match the user-defined attributes).

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SoC events trace

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DMA transfer profiling

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Statistics collector (performance probes)

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Computes traffic statistics within a user-defined window and periodically reports to the user

through the CT_STM interface

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Embedded in the L3_MAIN interconnect

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10 instances:

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1 instance dedicated to target (SDRAM) load monitoring

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9 instances dedicated to master latency monitoring

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EVE instrumentation

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Supported through a software message and system trace event (SMSET) module embedded in

the EVE subsystem

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ISS instrumentation

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Supported through system trace event (CTSET) module embedded in the ISS subsystem

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Power-management events profiling (PM instrumentation [PMI])

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Monitoring major power-management events. The PM state changes are handled as generic

events and encapsulated in STP messages.

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Clock-management events profiling CM instrumentation [CMI]) for CM_CORE_AON clocks

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Monitoring major clock management events. The CM state changes are handled as generic

events and encapsulated in STP messages.

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One instances

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CM1 Instrumentation (CMI1) module mapped in the PD_CORE_AON power domain

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For more information, see section System Instrumentation in chapter On-Chip Debug Support of

the Device TRM.

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Performance monitoring

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Supported by subsystem counter timer module (SCTM) for IPU

For more information, see chapter On-Chip Debug Support of the device TRM.

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