DM505 datasheet(139/295 Pages) TI2

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gpmc_fclk

gpmc_clk

gpmc_csi

gpmc_ben0

gpmc_

ben

gpmc_

_ale

advn

gpmc_wen

gpmc_ad[15:0]

gpmc_waitj

DIR

Address (MSB)

Valid Address (LSB)

Data OUT

OUT

FA0

FA1

FA9

FA10

FA3

FA25

FA29

FA12

FA27

FA28

FA0

FA10

GPMC_12

gpmc_a27

gpmc_a[10:1]

139

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Figure 5-33. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)

(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.

(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal

direction on the GPMC data bus.

5.9.6.6.3 GPMC/NAND Flash Interface Asynchronous Timing

Table 5-39 and Table 5-40 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-34, Figure 5-35, Figure 5-36 and Figure 5-37).

Table 5-39. GPMC/NAND Flash Interface Timing Requirements(1)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GNF12

tacc(DAT)

Data maximum access time (GPMC_FCLK Cycles)

cycles

tsu(DV-OEH)

Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high

1.9

th(OEH-DV)

Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high

(1) J = AccessTime × (TimeParaGranularity + 1)

Table 5-40. GPMC/NAND Flash Interface Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tr(DO)

Rising time, gpmc_ad[15:0] output data

0.447

4.067

tf(DO)

Fallling time, gpmc_ad[15:0] output data

0.43

4.463

GNF0

tw(nWEV)

Pulse duration, gpmc_wen valid time

A (1)

GNF1

td(nCSV-nWEV)

Delay time, gpmc_cs[7:0] valid to gpmc_wen valid

B - 0.2 (2)

B + 2.0

(2)

DM505 Datasheet(PDF) 139 Page - Texas Instruments

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