DM505LRBABF datasheet(252/295 Pages) TI2

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252

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Complete stackup specifications are provided in Table 7-25.

Table 7-25. PCB Stackup Specifications

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PS21

PCB routing/plane layers

PS22

Signal routing layers

PS23

Full ground reference layers under DDR2 routing region(1)

PS24

Full vdds_ddrx power reference layers under the DDR2 routing

region(1)

PS25

Number of reference plane cuts allowed within DDR routing region(2)

PS26

Number of layers between DDR2 routing layer and reference plane(3)

PS27

PCB routing feature size

Mils

PS28

PCB trace width, w

Mils

PS29

Single-ended impedance, Zo

Ω

PS210

Impedance control(4)

Z-5

Z+5

Ω

(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers. A full ground reference layer should be placed adjacent to each DDR routing

layer in PCB stack up.

(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4) Z is the nominal singled-ended impedance selected for the PCB specified by PS29.

DM505LRBABF Datasheet(PDF) 252 Page - Texas Instruments

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