DM505LRBABF datasheet(254/295 Pages) TI2

254 / 295 page

PCB_DDR2_4

Device

DDR2 Controller

254

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.8.2.2.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2

keepout region is defined for this purpose and is shown in Figure 7-41. The size of this region varies with

the placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 7-26.

The region shown in Table 7-26 should encompass all the DDR2 circuitry and varies depending on

placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keepout

region. Non-DDR2 signals may be routed in the region, provided they are routed on layers separated from

DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this

region. In addition, the vdds_ddrx power plane should cover the entire keepout region. Routes for the two

DDR interfaces must be separated by at least 4x; the more separation, the better.

Figure 7-41. DDR2 Keepout Region

7.8.2.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 7-27 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk

bypass capacitance may be needed for other circuitry.

Table 7-27. Bulk Bypass Capacitors

NO.

PARAMETER

MIN

TYP

MAX

UNIT

BC21

vdds_ddrx bulk bypass capacitor (

≥1µF) count(1)

Devices

BC22

vdds_ddrx bulk bypass total capacitance

μF

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-

speed (HS) bypass capacitors and DDR2 signal routing.

7.8.2.2.7 High-Speed Bypass Capacitors

TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and

placement is optimal for a given implementation. This section provides guidelines that can serve as a

good starting point.

DM505LRBABF Datasheet(PDF) 254 Page - Texas Instruments

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