DM505LRBABF datasheet(258/295 Pages) TI2

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PCB_DDR2_7

DDR2 Controller

258

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Table 7-32. CK and ADDR_CTRL Routing Specification (continued)

NO.

PARAMETER

MIN

MAX

UNIT

RSC210

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(2)

(1) Series terminator, if used, should be located closest to the Device.

(2) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) This is the longest routing length of the CK and ADDR_CTRL net classes.

Figure 7-44 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended. The termination resistor should be placed

near the processor.

Figure 7-44. DQS and DQ Routing and Topology

Table 7-33. DQS and DQ Routing Specification

NO.

PARAMETER

MIN

MAX

UNIT

RSDQ21

Center-to-center DQS-DQSn spacing in E0|E1|E2|E3

RSDQ22

DQS-DQSn skew in E0|E1|E2|E3

RSDQ23

Center-to-center DQS to other DDR2 trace spacing(1)

RSDQ24

DQS/DQ trace length (2)(3)(4)

325

RSDQ25

DQ-to-DQS skew mismatch(2)(3)(4)

RSDQ26

DQ-to-DQ skew mismatch(2)(3)(4)

RSDQ27

DQ-to-DQ/DQS via count mismatch(2)(3)(4)

Vias

RSDQ28

Center-to-center DQ to other DDR2 trace spacing(1)(5)

RSDQ29

Center-to-center DQ to other DQ trace spacing(1)(6)(7)

RSDQ210

DQ/DQS E skew mismatch(2)(3)(4)

(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs) per DDR EMIF used.

(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS

(4 DQSs) per DDR EMIF used.

(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data

byte1.

(5) DQs from other DQS domains are considered other DDR2 trace.

(6) DQs from other data bytes are considered other DDR2 trace.

(7) This is the longest routing distance of each of the DQS and DQ net classes.

7.9

DDR3 Board Design and Layout Guidelines

DM505LRBABF Datasheet(PDF) 258 Page - Texas Instruments

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