DM505LRBABF datasheet(260/295 Pages) TI2

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260

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

7.9.2.3

DDR3 Interface Schematic

7.9.2.3.1 32-Bit DDR3 Interface

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 7-46 and show the schematic connections for 32-bit interfaces

using x16 devices.

7.9.2.3.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 7-

46); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off

the ddrx_dqsi pins to ground via a 1k-

Ω resistor and to tie off the ddrx_dqsni pins to the corresponding

vdds_ddrx supply via a 1k-

Ω resistor. This needs to be done for each byte not used. Although these

signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection

against external electrical noise causing activity on the signals.

The vdds_ddr and vdds18v_ddrx power supply pins need to be connected to their respective power

supplies even if upper data byte lanes are not being used. All other DDR interface pins can be left

unconnected. Note that the supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or

not used.

DM505LRBABF Datasheet(PDF) 260 Page - Texas Instruments