DM505LRBABF datasheet(257/295 Pages) TI2

257 / 295 page

PCB_DDR2_6

DDR2 Controller

A’

PCB_DDR2_5

DDR2 Controller

VREF Bypass Capacitor

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to

accomodate via congestion for short

distances is also acceptable. Best

performance is obtained if the width

of VREF is maximized.

VREF Nominal Max Trace

width is 20 mils

1 K Ω 1%

vdds_ddrx

(A)

VREF

0.1 µF

1 K Ω 1%

A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.

257

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

Submit Documentation Feedback

Applications, Implementation, and Layout

Figure 7-42. VREF Routing and Topology

7.8.2.3

DDR2 CK and ADDR_CTRL Routing

Figure 7-43 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

point to point connection with required skew matching.

Figure 7-43. CK and ADDR_CTRL Routing and Topology

Table 7-32. CK and ADDR_CTRL Routing Specification

NO.

PARAMETER

MIN

MAX

UNIT

RSC21

Center-to-center ddrx_ck - ddrx_nck spacing

RSC22

ddrx_ck / ddrx_nck skew

RSC25

Center-to-center CK to other DDR2 trace spacing(2)

RSC26

CK/ADDR_CTRL trace length(3)

680

RSC27

ADDR_CTRL-to-CK skew mismatch

RSC28

ADDR_CTRL-to-ADDR_CTRL skew mismatch

RSC29

Center-to-center ADDR_CTRL to other DDR2 trace spacing(2)

DM505LRBABF Datasheet(PDF) 257 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 257 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL