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DM505LRBABF Datasheet(PDF) 261 Page - Texas Instruments

Part # DM505LRBABF
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505LRBABF Datasheet(HTML) 261 Page - Texas Instruments

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DQ15
DQ8
UDM
UDQS
UDQS
DQ7
DQ0
LDM
LDQS
LDQS
CK
DQ15
UDM
UDQS
UDQS
ddrx_d31
ddrx_d24
16-Bit DDR3
Devices
0.1 µF
0.1 µF
32-bit DDR3 EMIF
ddrx_dqm3
ddrx_dqs3
ddrx_dqsn3
ddrx_d23
ddrx_d16
ddrx_dqm2
ddrx_dqs2
ddrx_dqsn2
ddrx_d15
ddrx_d8
ddrx_dqm1
ddrx_dqs1
ddrx_dqsn1
ddrx_d7
ddrx_d0
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_ck
ddrx_nck
ddrx_odt0
ddrx_csn0
ddrx_ba0
ddrx_ba1
ddrx_ba2
ddrx_a0
ddrx_a15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
8
8
8
8
16
DQ8
DQ7
D08
LDM
LDQS
LDQS
CK
ODT
BA1
BA0
BA2
CS
A0
A15
CAS
RAS
WE
RST
CKE
ZQ
VREFDQ
VREFCA
ZQ
CK
CK
ODT
BA1
BA0
BA2
CS
A0
A15
CAS
RAS
WE
RST
CKE
ZQ
VREFDQ
VREFCA
ZQ
Zo
Zo
Zo
Zo
DDR_VREF
DDR_VTT
DDR_1V5
Termination is required. See terminator comments.
Zo
Value determined according to the DDR memory device data sheet.
ZQ
0.1 µF
261
DM505
www.ti.com
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
Submit Documentation Feedback
Applications, Implementation, and Layout
Copyright © 2016–2018, Texas Instruments Incorporated
Figure 7-46. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices



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