DM505LRBABF datasheet(262/295 Pages) TI2

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DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.9.2.4

Compatible JEDEC DDR3 Devices

Table 7-36 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths.

Table 7-36. Compatible JEDEC DDR3 Devices

PARAMETER

CONDITION

MIN

MAX

UNIT

JEDEC DDR3 device speed grade(1)

DDR clock rate = 400MHz

DDR3-800

DDR3-1600

400MHz< DDR clock rate

≤ 533MHz

DDR3-1066

DDR3-1600

JEDEC DDR3 device bit width

x16

Bits

JEDEC DDR3 device count(2)

Devices

(1) Refer to Table 7-34 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of

supported DDR clock rates.

(2) For valid DDR3 device configurations and device counts, see Table 7-35 DDR3 Device Combinations.

7.9.2.5

PCB Stackup

The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 7-37.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI

performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in

Table 7-38.

Table 7-37. Six-Layer PCB Stackup Suggestion

LAYER

TYPE

DESCRIPTION

Signal

Top routing mostly vertical

Plane

Ground

Plane

Split power plane

Plane

Split power plane or Internal routing

Plane

Ground

Signal

Bottom routing mostly horizontal

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