DM505LRBABF datasheet(266/295 Pages) TI2

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266

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Table 7-40. Bulk Bypass Capacitors

NO.

PARAMETER

MIN

MAX

UNIT

vdds_ddrx bulk bypass capacitor count(1)

Devices

vdds_ddrx bulk bypass total capacitance

μF

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-

speed (HS) bypass capacitors and DDR3 signal routing.

7.9.2.9

High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,

and processor/DDR ground connections. Table 7-41 contains the specification for the HS bypass

capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible.

2. Minimize the distance from the bypass cap to the pins/balls being bypassed.

3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.

4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest

hole size via possible.

5. Minimize via sharing. Note the limites on via sharing shown in Table 7-41.

Table 7-41. High-Speed Bypass Capacitors

NO.

PARAMETER

MIN

TYP

MAX

UNIT

HS bypass capacitor package size(1)

0201

0402

10 Mils

Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)

400

Mils

Processor HS bypass capacitor count per vdds_ddrx rail(12)

See Table 7-3 and (11)

Devices

Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)

See Table 7-3 and (11)

μF

Number of connection vias for each device power/ground ball(5)

Vias

Trace length from device power/ground ball to connection via(2)

Mils

Distance, HS bypass capacitor to DDR device being bypassed(6)

150

Mils

DDR3 device HS bypass capacitor count(7)

Devices

DDR3 device HS bypass capacitor total capacitance(7)

0.85

μF

Number of connection vias for each HS capacitor(8)(9)

Vias

Trace length from bypass capacitor connect to connection via(2)(9)

100

Mils

Number of connection vias for each DDR3 device power/ground ball(10)

Vias

Trace length from DDR3 device power/ground ball to connection via(2)(8)

Mils

(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.

(2) Closer/shorter is better.

(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.

(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,

between the DDR interfaces on the package.

(5) See the Via Channel™ escape for the processor package.

(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.

(7) Per DDR3 device.

(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of

vias is permitted on the same side of the board.

(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the

connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s

guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.

(12) For more information, see Section 7.3, Core Power Domains.

DM505LRBABF Datasheet(PDF) 266 Page - Texas Instruments

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