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DM505LRBABF Datasheet(PDF) 269 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 269 Page - Texas Instruments |
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269 / 295 page ![]() = Rtt A2 A3 A4 AT Vtt SPRS91v_PCB_DDR3_09 = Rcp Rcp Cac DDR_1V5 0.1 µF A2 A3 A4 A2 A3 A4 AT AT SPRS91v_PCB_DDR3_08 269 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Figure 7-51. CK Routing for Three Single-Side DDR3 Devices Figure 7-52. ADDR_CTRL Routing for Three Single-Side DDR3 Devices To save PCB space, the two DDR3 memories may be mounted as one mirrored pair at a cost of increased routing and assembly complexity. Figure 7-53 and Figure 7-54 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a pair configuration. |
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