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DM505LRBABF Datasheet(PDF) 272 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 272 Page - Texas Instruments |
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272 / 295 page ![]() = Rtt A2 A3 AT Vtt SPRS91v_PCB_DDR3_15 = Rcp Rcp Cac DDR_1V5 0.1 µF A2 A3 AT A2 A3 AT SPRS91v_PCB_DDR3_14 272 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Figure 7-57. CK Routing for Two Single-Side DDR3 Devices Figure 7-58. ADDR_CTRL Routing for Two Single-Side DDR3 Devices To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 7-59 and Figure 7-60 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration. |
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