DM505LRBABF datasheet(276/295 Pages) TI2

Part #	DM505LRBABF

Description	DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0

PDF	295 Pages

Scroll/Zoom	100%

Manufacturer	TI2 [Texas Instruments]

Direct Link	https://www.ti.com

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276 / 295 page

DQSn+

DQSn-

n = 0, 1, 2

Routed Differentially

DQS

SPRS91v_PCB_DDR3_24

Processor

DQ and DM

IO Buffer

DDR

DQ and DM

IO Buffer

n = 0, 1, 2, 3

SPRS91v_PCB_DDR3_23

Processor

DQS

IO Buffer

DDR

DQS

IO Buffer

Routed Differentially

n = 0, 1, 2, 3

DQSn-

DQSn+

SPRS91v_PCB_DDR3_22

276

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 7-65

and Figure 7-66 show these topologies.

Figure 7-65. DQS Topology

Figure 7-66. DQ/DM Topology

7.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices

Figure 7-67 and Figure 7-68 show the DQS and DQ/DM routing.

Figure 7-67. DQS Routing With Any Number of Allowed DDR3 Devices

DM505LRBABF Datasheet(PDF) 276 Page - Texas Instruments