DM505LRBABF datasheet(280/295 Pages) TI2

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DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Table 7-44. CK and ADDR_CTRL Routing Specification(2)(3) (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

CARS321

CK center-to-center spacing(11)(12)

CARS322

CK spacing to other net(9)

CARS323

Rcp(13)

Zo-1

Zo+1

CARS324

Rtt(13)(14)

Zo-5

Zo+5

(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of

rise time and fall time confirms desired operation.

(2) The use of vias should be minimized.

(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump

between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.

(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).

(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(6) While this length can be increased for convenience, its length should be minimized.

(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(8) CK net class only.

(9) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended

impedance, Zo.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal

propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.

7.9.2.15.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are three

DQLMs, DQLM0-DQLM2. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 7-71 shows this distance for

four loads. It is from this distance that the specifications on the lengths of the transmission lines for the

data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 7-45.

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