DM505LRBABF datasheet(277/295 Pages) TI2

277 / 295 page

n = 0, 1, 2

DQ and DM

SPRS91v_PCB_DDR3_25

277

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Figure 7-68. DQ/DM Routing With Any Number of Allowed DDR3 Devices

7.9.2.15 Routing Specification

7.9.2.15.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 7-69 and Figure 7-70 show

this distance for three loads and two loads, respectively. It is from this distance that the specifications on

the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly

for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net

class. For CK and ADDR_CTRL routing, these specifications are contained in Table 7-44.

DM505LRBABF Datasheet(PDF) 277 Page - Texas Instruments