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DM505LRBABF Datasheet(PDF) 274 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 274 Page - Texas Instruments |
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274 / 295 page  A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers AT Vtt Address and Control Terminator Rtt SPRS91v_PCB_DDR3_19 A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffer Routed as Differential Pair AT Rcp Clock Parallel Terminator A1 A2 AT Rcp Cac DDR_1V5 0.1 µF + – + – SPRS91v_PCB_DDR3_18 274 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Figure 7-61. CK Topology for One DDR3 Device Figure 7-62. ADDR_CTRL Topology for One DDR3 Device 7.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device Figure 7-63 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 7-64 shows the corresponding ADDR_CTRL routing. |
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