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DM505LRBABF Datasheet(PDF) 271 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 271 Page - Texas Instruments |
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271 / 295 page  A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers A3 AT Vtt Address and Control Terminator Rtt SPRS91v_PCB_DDR3_13 A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffers Routed as Differential Pair A3 AT Rcp Clock Parallel Terminator A1 A2 A3 AT Rcp Cac DDR_1V5 0.1 µF + – + – + – SPRS91v_PCB_DDR3_12 271 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Figure 7-55. CK Topology for Two DDR3 Devices Figure 7-56. ADDR_CTRL Topology for Two DDR3 Devices 7.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 7-57 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-58 shows the corresponding ADDR_CTRL routing. |
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