DM505LRBABF datasheet(268/295 Pages) TI2

268 / 295 page

Processor

Address and Control

Output Buffer

DDR Address and Control Input Buffers

Vtt

Address and Control

Terminator

Rtt

SPRS91v_PCB_DDR3_07

Processor

Differential Clock

Output Buffer

DDR Differential CK Input Buffers

Routed as Differential Pair

Rcp

Clock Parallel

Terminator

Rcp

Cac

DDR_1V5

0.1 µF

–

+ –

SPRS91v_PCB_DDR3_06

268

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.9.2.13.1 Three DDR3 Devices

Three DDR3 devices are supported on the DDR EMIF consisting of two x16 DDR3 devices and one

device for ECC, arranged as one bank (CS). These three devices may be mounted on a single side of the

PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and

parts on the backside of the PCB.

7.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices

Figure 7-49 shows the topology of the CK net classes and Figure 7-50 shows the topology for the

corresponding ADDR_CTRL net classes.

Figure 7-49. CK Topology for Three DDR3 Devices

Figure 7-50. ADDR_CTRL Topology for Three DDR3 Devices

7.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices

Figure 7-51 shows the CK routing for three DDR3 devices placed on the same side of the PCB. Figure 7-

52 shows the corresponding ADDR_CTRL routing.

DM505LRBABF Datasheet(PDF) 268 Page - Texas Instruments

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