DM505LRBABF datasheet(267/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.9.2.9.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. These are returns for signal current, the signal via size may be used for these capacitors.

7.9.2.10 Net Classes

Table 7-42 lists the clock net classes for the DDR3 interface. Table 7-43 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 7-42. Clock Net Class Definitions

CLOCK NET CLASS

processor PIN NAMES

ddrx_ck/ddrx_nck

DQS0

ddrx_dqs0 / ddrx_dqsn0

DQS1

ddrx_dqs1 / ddrx_dqsn1

DQS2(1)

ddrx_dqs2 / ddrx_dqsn2

DQS3(1)

ddrx_dqs3 / ddrx_dqsn3

(1) Only used on 32-bit wide DDR3 memory systems.

Table 7-43. Signal Net Class Definitions

SIGNAL NET CLASS

ASSOCIATED CLOCK

NET CLASS

processor PIN NAMES

ADDR_CTRL

ddrx_ba[2:0], ddrx_a[15:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,

ddrx_cke, ddrx_odti

DQ0

DQS0

ddrx_d[7:0], ddrx_dqm0

DQ1

DQS1

ddrx_d[15:8], ddrx_dqm1

DQ2(1)

DQS2

ddrx_d[23:16], ddrx_dqm2

DQ3(1)

DQS3

ddrx_d[31:24], ddrx_dqm3

(1) Only used on 32-bit wide DDR3 memory systems.

7.9.2.11 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

7.9.2.12 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

7.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew

between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.

The following subsections show the topology and routing for various DDR3 configurations for CK and

ADDR_CTRL. The figures in the following subsections define the terms for the routing specification

detailed in Table 7-44.

DM505LRBABF Datasheet(PDF) 267 Page - Texas Instruments

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