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DM505LRBABF Datasheet(PDF) 273 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 273 Page - Texas Instruments |
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273 / 295 page  = Rtt A2 A3 AT Vtt SPRS91v_PCB_DDR3_17 = Rcp Rcp Cac DDR_1V5 0.1 µF A2 A3 AT A2 A3 AT SPRS91v_PCB_DDR3_16 273 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Figure 7-59. CK Routing for Two Mirrored DDR3 Devices Figure 7-60. ADDR_CTRL Routing for Two Mirrored DDR3 Devices 7.9.2.13.3 One DDR3 Device A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as one bank (CS), 16 bits wide. 7.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 7-61 shows the topology of the CK net classes and Figure 7-62 shows the topology for the corresponding ADDR_CTRL net classes. |
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