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DM505LRBABF Datasheet(PDF) 283 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 283 Page - Texas Instruments |
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283 / 295 page  283 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated Table 7-46 and Table 7-47 present the Static and Dynamic CVIDEO / SD-DAC TV analog composite output specifications Table 7-46. Static CVIDEO/SD-DAC Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Current Setting Resistor (RSET) Normal Mode 4653 4700 4747 Ω TVOUT Bypass Mode 9900 10000 10100 Ω Output resistor between cvideo_tvout and cvideo_vfb pins (ROUT) Normal Mode 2673 2700 2727 Ω TVOUT Bypass Mode N/A Load Resistor (RLOAD) Normal Mode 75-Ω Inside the Display TVOUT Bypass Mode 1485 1500 1515 Ω AC-Coupling Capacitor (Optional) [CAC] Normal Mode 220 uF TVOUT Bypass Mode See External Amplifier Specification Total Capacitance from cvideo_tvout to vssa_dac Normal Mode 300 pF TVOUT Bypass Mode N/A Resolution 10 Bits Integral Non-Linearity (INL), Best Fit Normal Mode -4 4 LSB TVOUT Bypass Mode -1 1 LSB Differential Non-Linearity (DNL) Normal Mode -2.5 2.5 LSB TVOUT Bypass Mode -1 1 LSB Full-Scale Output Voltage Normal Mode (RLOAD = 75 Ω) 1.3 V TVOUT Bypass Mode (RLOAD = 1.5 kΩ) 0.7 V Full-Scale Output Current Normal Mode N/A TVOUT Bypass Mode 470 uA Gain Error Normal Mode (Composite) and TVOUT Bypass Mode -10 10 %FS Normal Mode (S-Video) -20 20 %FS Gain Mismatch (Luma-to-Chroma) Normal Mode (Composite) N/A Normal Mode (S-Video) -10 10 % Output Impedance Looking into cvideo_tvout nodes 75 Ω Table 7-47. Dynamic CVIDEO/SD-DAC Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Update Rate (FCLK) 54 60 MHz Signal Bandwidth 3 dB 6 MHz Spurious-Free Dynamic Range (SFDR) within bandwidth FCLK = 54 MHz, FOUT = 1 MHz 50 dBc Signal-to-Noise Ration (SNR) FCLK = 54 MHz, FOUT = 1 MHz 54 dB Power Supply Rejection (PSR) Normal Mode, 100 mVpp @ 6 MHz on vdda_dac 6 dB TVOUT Bypass Mode, 100 mVpp @ 6 MHz on vdda_dac 20 |
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