DM505LRBABF datasheet(259/295 Pages) TI2

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DDR_CLK

SPRS91v_PCB_DDR3_01

259

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.9.1

DDR3 General Board Layout Guidelines

To help ensure good signaling performance, consider the following board design guidelines:

•

Avoid crossing splits in the power plane.

•

Use the widest trace that is practical between decoupling capacitors and memory module.

•

Maintain a single reference

•

Minimize ISI by keeping impedances matched.

•

Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.

•

Keep the stub length as short as possible.

•

Add additional spacing for on-clock and strobe nets to eliminate crosstalk.

•

Maintain a common ground reference for all bypass and decoupling capacitors.

•

Take into account the differences in propagation delays between microstrip and stripline nets when

evaluating timing constraints.

7.9.2

DDR3 Board Design and Layout Guidelines

7.9.2.1

Board Designs

TI only supports board designs using DDR3 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 7-34 and

Figure 7-45.

Table 7-34. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Controller

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CLK)

Cycle time, DDR_CLK

1.875

2.5(1)

(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and

operating frequency (see the DDR3 memory device data sheet).

Figure 7-45. DDR3 Memory Controller Clock Timing

7.9.2.2

DDR3 Device Combinations

There are several possible combinations of device counts and single- or dual-side mounting, Table 7-35

summarizes the supported device configurations.

Table 7-35. Supported DDR3 Device Combinations

NUMBER OF DDR3

DEVICES

DDR3 DEVICE WIDTH

(BITS)

ECC DEVICE WIDTH

(BITS)

MIRRORED?

DDR3 EMIF WIDTH

(BITS)

1x16

2x8

Y(1)

2x16

Y(1)

1x16

1x8

2x8

1x8

2x16

1x8

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