DM505LRBABF datasheet(256/295 Pages) TI2

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DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.8.2.2.8 Net Classes

Table 7-29 lists the clock net classes for the DDR2 interface. Table 7-30 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 7-29. Clock Net Class Definitions

CLOCK NET CLASS

PIN NAMES

ddrx_ck / ddrx_nck

DQS0

ddrx_dqs0 / ddrx_dqsn0

DQS1

ddrx_dqs1 / ddrx_dqsn1

DQS2(1)

ddrx_dqs2 / ddrx_dqsn2

DQS3(1)

ddrx_dqs3 / ddrx_dqsn3

(1) Only used on 32-bit wide DDR2 memory systems.

Table 7-30. Signal Net Class Definitions

SIGNAL NET CLASS

ASSOCIATED CLOCK

NET CLASS

PIN NAMES

ADDR_CTRL

ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,

ddrx_cke, ddrx_odti

DQ0

DQS0

ddrx_d[7:0], ddrx_dqm0

DQ1

DQS1

ddrx_d[15:8], ddrx_dqm1

DQ2(1)

DQS2

ddrx_d[23:16], ddrx_dqm2

DQ3(1)

DQS3

ddrx_d[31:24], ddrx_dqm3

(1) Only used on 32-bit wide DDR2 memory systems.

7.8.2.2.9 DDR2 Signal Termination

Signal terminators are NOT required in CK, ADDR_CTRL, and DATA net classes. Serial terminators may

be used to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are integrated

on the data byte net classes. They should be enabled to ensure signal integrity. Table 7-31 shows the

specifications for the series terminators.

Table 7-31. DDR2 Signal Terminations

NO.

PARAMETER

MIN

TYP

MAX

UNIT

ST21

CK net class(1)(2)

Ω

ST22

ADDR_CTRL net class(1) (2)(3)(4)

Ω

ST23

Data byte net classes (DQS0-DQS3, DQ0-DQ3)(5)

Ω

(1) Only series termination is permitted, parallel or SST specifically disallowed on board.

(2) Only required for EMI reduction.

(3) Terminator values larger than typical only recommended to address EMI issues.

(4) Termination value should be uniform across net class.

(5) No external terminations allowed for data byte net classes ODT is to be used.

7.8.2.2.10 VREF Routing

VREF (ddrx_vref0) is used as a reference by the input buffers of the DDR2 memories. VREF is intended

to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in

Figure 7-39. Other methods of creating VREF are not recommended. Figure 7-42 shows the layout

guidelines for VREF.

DM505LRBABF Datasheet(PDF) 256 Page - Texas Instruments

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