DM505LRBABF datasheet(253/295 Pages) TI2

253 / 295 page

PCB_DDR2_3

DDR2 Controller

DDR2

Memory

253

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.8.2.2.4 Placement

Figure 7-40 shows the required placement for the Device as well as the DDR2 devices. The dimensions

for this figure are defined in Table 7-26. The placement does not restrict the side of the PCB on which the

devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and

allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device is omitted

from the placement.

Figure 7-40. Device and DDR2 Device Placement

Table 7-26. Placement Specifications DDR2

NO.

PARAMETER

MIN

MAX

UNIT

KOD21

1100

Mils

KOD22

500

Mils

KOD24

DDR2 keepout region (1)

KOD25

Clearance from non-DDR2 signal to DDR2 keepout region (2) (3)

(1) DDR2 keepout region to encompass entire DDR2 routing area.

(2) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR2 and should be

separated by this specification.

DM505LRBABF Datasheet(PDF) 253 Page - Texas Instruments