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TDA2SA Datasheet(PDF) 150 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 150 Page - Texas Instruments |
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150 / 427 page  150 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-9. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name McSPI3 SPI3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI3_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER McSPI4 SPI4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI4_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER MMC1 MMC1_CLK_32K Func 0.032 L3INIT_32K_GFCLK FUNC_32K_CLK OSC1 MMC1_FCLK Func 192 MMC1_GFCLK FUNC_192M_CLK DPLL_PER 128 FUNC_256M_CLK DPLL_PER MMC1_ICLK1 Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE MMC1_ICLK2 Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE MMC2 MMC2_CLK_32K Func 0.032 L3INIT_32K_GFCLK FUNC_32K_CLK OSC1 MMC2_FCLK Func 192 MMC2_GFCLK FUNC_192M_CLK DPLL_PER 128 FUNC_256M_CLK DPLL_PER MMC2_ICLK1 Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE MMC2_ICLK2 Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE MMC3 MMC3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE MMC3_CLK_32K Func 0.032 L4PER_32K_GFCLK FUNC_32K_CLK OSC1 MMC3_FCLK Func 48 MMC3_GFCLK FUNC_192M_CLK DPLL_PER 192 MMC4 MMC4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE MMC4_CLK_32K Func 0.032 L4PER_32K_GFCLK FUNC_32K_CLK OSC1 MMC4_FCLK Func 48 MMC4_GFCLK FUNC_192M_CLK DPLL_PER 192 MMU_EDMA MMU1_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE MMU_PCIESS MMU2_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE MPU MPU_CLK Int & Func MPU_CLK MPU_GCLK MPU_GCLK DPLL_MPU MPU_EMU_DBG FCLK Int 38.4 EMU_SYS_CLK SYS_CLK1 OSC1 MPU_GCLK DPLL_MPU OCMC_RAM1 OCMC1_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE OCMC_RAM2 OCMC2_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE OCMC_RAM3 OCMC3_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE OCMC_ROM OCMC_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE OCP_WP_NOC PICLKOCPL3 Int 266 L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE OCP2SCP1 L4CFG1_ADAPTE R_CLKIN Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE OCP2SCP2 L4CFG2_ADAPTE R_CLKIN Int 133 L4CFG_L4_GICLK CORE_X2_CLK DPLL_CORE OCP2SCP3 L4CFG3_ADAPTE R_CLKIN Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE |
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